1. Field of the Invention
This invention relates to a field-effect transistor and a production method therefor, and more particularly to a field-effect transistor in which gate, source and drain electrodes are disposed on two semiconductor regions with different impurity concentrations, and to a production method therefor.
2. Description of the Related Art
The technical level of finely fabricated semiconductors is indicated by transistor gate length. The gate length has been in the order of submicrons for several years. In the field of semiconductor devices, in order to enable high levels of integration, the aim of establishing a technology for mass-production of semiconductor devices with a gate length of less than 0.1 micron will be continued.
Referring to the accompanying drawings, description will briefly be given of a process of producing a GaAs field-effect transistor (GaAs FET) by a conventional common method, as well as the structure of the FET. FIG. 13 through FIG. 16 show a process of forming an FET on a GaAs substrate according to the method suggested in ED81-14 of Institute of Electronics Communication Engineers of Japan, or a monthly magazine Semiconductor World, June 1987, pp. 86-93.
FIG. 13 shows a gate electrode 4 formed on an n layer 2 which has been formed in advance by ion implantation.
FIG. 14 shows that n.sup.+ layer ion implantation is carried out with the gate electrode 4 as the mask. The n layer 2 remains below the gate electrode 4, but other areas are replaced with n.sup.+ layers 6. At this time, however, the n.sup.+ layers 6 are inert, and an SiO.sub.2 protective film 8 is formed, as shown in FIG. 15, followed by annealing at about 800.degree. C.
Lastly, FIG. 16 shows that the protective film 8 is removed, and a source electrode 10 and a drain electrode 12 are formed.
Thus, a GaAs FET is produced. In the above process, making a gate length as short as possible provides high speed and high integration. An IC produced by the above ion implantation has a planar structure and excels in control of a threshold voltage V.sub.th, SO that it has various uses such as a large scale logical IC.
According to the above process, the GaAs FET can be produced easily. However, problems due to a short channel effect arise because the gate length is now in the order of submicrons. This problem will be described with reference to FIG. 17.
FIG. 17 shows the structure of the FET shown in FIG. 16, also showing a view of an energy band taken along line B.
Since the n layer 2 just below the gate electrode is very narrow, the short channel effect, which is almost negligible in a region of 1 micron or more, suddenly becomes apparent, deteriorating the characteristics of the FET. The short channel effect roughly has the following two causes.
[Cause 1]
When the ion implantation for the n.sup.+ layer 6 and the annealing for activation are carried out, implanted dopant is dispersed toward the n layer 2, causing carrier distribution within the channel broad.
[Cause 2]
A tunnel current of n.sup.+ /i/n.sup.+ flows immediately below the channel.
Cause 1 is naturally expected as long as a conventional production method is employed. Cause 2 is also an unavoidable problem due to the structure of a conventional FET. The magnitude of the tunnel current is substantially proportional to a source-to-drain voltage V.sub.DS exponentially. With the increase of drain conductance due to this current, the channel thickness is substantially increased, and K-value is decreased.
The deterioration of the characteristics will be described with reference to FIG. 18 and FIG. 19. FIG. 18 is a graph showing the relation between the gate length and V.sub.th of the FET shown in FIG. 17, and FIG. 19 shows the relation between the gate length and the K-value of the same FET.
It can be seen from FIG. 18 that the absolute value of V.sub.th to be given increases as the gate length decreases, and controllability of the FET deteriorates considerably when the gate length is 0.5 micron. On the other hand, it can be seen from FIG. 19 that the K-value is sharply decreased when the gate length becomes 0.7 micron or below.
In view of the above, it can be seen that the FET having a gate length of submicrons, particularly less than 0.5 micron, inherently has its conventional structure limited.